For example, in the dynamic random access memory (DRAM), information is stored by accumulating electric charges in a capacitor via memory-cell transistor. In DRAM, the area the memory cell occupies decreases as integration increases and miniaturization advances.
As a conventional DRAM memory cell configuration, for example, the following one can be mentioned set forth in: Jong-Wan Jung and seven others: A fully working 0.14 μm DRAM technology with polymetal (W/WNx/Poly-Si) gate), “IEDM (International Electron Devices Meeting) 2000 Technical Digest,” p. 365-368. That is, the memory cell configurations shown in FIG. 28 through FIG. 30 are available. FIG. 28 is a drawing of one example showing memory cell layout configuration in semiconductor memory devices of conventional technologies studies as the premise of the present invention. FIG. 29 is a drawing of one example showing cross-sectional configuration taken on line A-A′ of FIG. 28. FIG. 30 is a drawing of an equivalent circuit of FIG. 28. As shown in FIG. 30, DRAM according to the conventional technology has a memory cell MC at a desired intersection between a word line WL and a bit line BL in a memory cell array MCA, and one memory cell MC comprises one memory cell transistor M1 and one capacitor Cs.
The layout of memory cell MCA has diffusion layer regions DIFF, respectively, between two gates GM which become the word lines WL and on both sides in an island-shape active region AA as shown in FIG. 28. Of these, the diffusion layer region DIFF between two gates GM (word lines WL) is connected to bit line BL via bit-line contact BC. On the other hand, the diffusion layer regions DIFF on both sides of two gates GM are storage nodes SN and are connected to capacitors CAP (not illustrated) via storage node contacts SC.
The portion other than this active region AA is the isolation region STI formed with insulator. By this, the diffusion layer region DIFF (SN) which becomes storage node SN has the three sides excluding the side that comes in contact with the bit line contact BC of the four sides which form the boundary section covered with the isolation region STI. In addition, the cross-sectional structure of memory cell array MCA has two gates GM (word wires WL) between adjacent capacitors CAP as shown in FIG. 29, and the clearance between two diffusion layer regions DIFF (SN) that form two memory cell storage nodes SN is separated by the isolation region STI.
The memory cell layout shown in FIG. 28 is used in the configuration of so-called folded bit line. With respect to the size of the memory cell MC, let ½ the word line pitch be the feature size F; then, both gate length and gate width W are F and the memory cell area S is expressed by S=4F (W+F). Consequently, when the gate size of memory cell transistor M1 is increased, the memory cell area S is increased by 4F2 each as the memory cell transistor gate width W is increased by F each, and the chip area increases accordingly.